To cope with pin multiplication, fine pitches, and increase in signal speed of semiconductor chips, used is a semiconductor device adopting flip-chip (FC) connection as amounting method with short wiring and connection lengths. The semiconductor chip has a solder bump formed on an electrode pad via a barrier metal layer. A wiring substrate to which the semiconductor chip is connected has a connecting pad corresponding to the electrode pad of the semiconductor chip and a preliminary solder layer formed on the connecting pad directly or via a barrier metal layer.
For the solder bump formed on the semiconductor chip and the preliminary solder layer formed on the wiring substrate, a Pb-free solder containing substantially no Pd is used. As the Pb-free solder, for example, a Sn alloy such as a Sn—Ag alloy, a Sn—Cu alloy, a Sn—Ag—Cu alloy, a Sn—Bi alloy or the like is used. The barrier metal layer mainly contains Ni and selected according to the compositions and the like of the solder bump and the preliminary solder layer. As the barrier metal layer, a stacked film such as, for example, Ni/Ti, Ni/Cu/Ti or the like is adopted.
Ag in the Sn—Ag alloy hardens the solder and therefore has an advantage of improving the connection strength by a solder connecting part (a melted solidified body of the solder bump and the preliminary solder layer) after FC connection. On the other hand, Ag decreases the creeping property of the solder connecting part and therefore cannot sufficiently relax the thermal stress generated in the solder bump based on the difference in thermal expansion coefficient between the semiconductor chip and the wiring substrate during FC connection. This causes a crack or delamination to easily occur in the semiconductor chip. Especially when a low dielectric constant insulating film (low-k film) capable of reducing the inter-wiring capacity is used for the interlayer insulating film of the semiconductor chip, the low-k film itself has a low strength and a low bonding strength with another film and therefore is susceptible to a crack or delamination.
Cu in the Sn—Cu alloy has advantages of improving the creeping property of the solder and relaxing the thermal stress generated in the solder bump. This makes it possible to suppress a crack and delamination of the semiconductor chip, particularly a crack and delamination of the low-k film. On the other hand, the solder is apt to embrittle because the crystal grains in the solder grow during relaxation of the thermal stress generated in the solder bump. This decreases the fatigue resistance of the solder connecting part. The decrease causes a crack or the like to occur in the solder connecting part when a thermal cycle test (TCT) is performed on the semiconductor device.
Ina connection structure between the semiconductor device (semiconductor package) and the wiring substrate, a solder connecting part formed of a Sn—Au—Ag—Cu alloy is known. The solder bump is generally formed by electrolytic plating of alloy, but the alloy plating solution is expensive and has short lifetime, leading to increased forming cost of the solder bump. Adoption of stacked plating (stacking of plating of constituent elements of alloy) at low cost to the formation of the solder bump is under consideration, but Ag plating is formed in a recessed shape and greatly varies in film thickness and therefore it is difficult to control a very low concentration of about several percents.